1. Field of the Invention
The invention relates generally to the field of random access memories and more particularly to improved "write" mode circuitry.
2. Related Applications
U.S. patent application Ser. No. 682,391 (FI9-83-052) "Improved Random Access Memory", filed 12-17-84 by G. J. Jordy and J. M. Mosley and of common assignee herewith. U.S. application Ser. No. 682,391 (FI9-83-052) filed 12-17-84 is incorporated herein by reference thereto fully and to the same extent as though the entire specification and drawings thereof were expressly set-forth herein.
U.S. patent application Ser. No. 625,426 entitled "Improved Gate Array Chip", filed June 28, 1984 by E. F. Culican et al and of common assignee herewith.
3. Background and Prior Art
In many prior art random access memory arrays the selected cell to be written is brought into the selected state by the proper voltages on its word/drain lines and first/second bit lines. It is known that maintaining a high voltage state on the selected first or second bit line for an indeterminate time can cause disturb conditions in subsequently selected cells. The prior art has addressed this problem in a variety of ways, each of which has its own drawbacks. One method is to use large voltage swings to increase noise immunity. But this requires higher supply voltages and uses more power. Other methods impose timing restrictions which impact performance and place additional burden on the user.
The solution to the problem in accordance with the invention is an improved random access memory which includes the provision of "self-limiting write circuit means".
The prior art includes numerous patents directed to random access memories and more specifically to techniques and circuitry for enhancing the speed and quality of the "write mode".
The following prior art patents are directed to random access memory circuits and related circuitry. It is to be appreciated that the following art is not necessarily the only, the best, or the most pertinent prior art.
U.S. Pat. No. 3,510,856 entitled "Grounding Switches For Differential Sense Amplifiers in Memory Systems" granted May 5, 1970 to J. M. Cline.
U.S. Pat. No. 3,848,236 entitled "Threshold Circuit" granted Nov. 12, 1974 to B. L. Troutman.
U.S. Pat. No. 4,092,551 entitled "A.C. Powered Speed Up Circuit" granted May 30, 1978 to D. D. Howard et al.
U.S. Pat. No. 4,319,344 entitled "Method And Circuit Arrangement For Discharging Bit Line Capacitances of an Integrated Semiconductor Memory" granted Mar. 9, 1982 to K. Heuber et al.
U.S. Pat. No. 4,321,490 entitled "Transistor Logic Output For Reduced Power Consumption And Increased Speed During Low to High Transition" granted Mar. 23, 1982 to R. W. Bechdolt.
U.S. Pat. No. 4,330,723 entitled "Transistor Logic Output Device For Diversion of Miller Current" granted May 18, 1982 to P. J. Griffith.
U.S. Pat. No. 4,366,558 entitled "Memory Device With Fast Word-Line-Discharging-Circuits" granted Dec. 28, 1982 to N. Homma et al.